Design and Performance Analysis of 32 × 32 Memory Array SRAM for Low-Power Applications

Computer memory comprises temporarily or permanently stored data and instructions, which are utilized in electronic digital computers. The opposite of serial access is Random Access Memory (RAM), where the accessed immediately for both reading writing operations. There has been a vast technological improvement, led to tremendous information on amount complexity that can be designed single chip. Small feature sizes, low power requirements, costs, great performance have emerged as essential attributes any component. Designers forced into sub-micron realm all these reasons, places leakage characteristics front centre. Many electrical parts, especially ones, made store data, emphasising need memory. largest factor consumption SRAM current. In this article, 1 KB array was created using CMOS technology supply voltage 0.6 volts employing 1-bit 6T cell. We developed with 1-bit, 32- × 32 configuration. structure implemented cell minimum current 18.65 pA an average delay 19 ns. 48.22 μW 385 read write proposed performed better than existing 8T 7T terms Using Cadence Virtuoso tool (Version IC6.1.8-64b.500.14) 22 nm technology, functionality verified.